This invention relates to improvements in a semiconductor memory device having an integrated injection logic (which is abbreviated hereinafter to "IIL") configuration including NPN transistors and PNP transistors in a composite form.
In order to fulfil the requirements of a high density and a high integration, semiconductor memory devices have been principally formed by employing MOS integrated circuits having MOS transistors assembled thereinto for the reasons that the isolation of elements involved is not required and the manufacturing steps are simple and so on. On the other hand, bipolar integrated circuits having bipolar transistors assembled thereinto have been infrequently employed to form semiconductor memory devices. However, when manufacturing bipolar integrated circuits, the control of base width is easy as compared with the control of the channel length of MOS transistors. This is accompanied by the facilitation of high speed production and also a decrease in problems concerning the production. If the problem of isolating the semiconductor elements involved from one another is solved, and if the manufacturing steps can be simplified then it is expected that bipolar integrated circuits will be widely used for semiconductor memory devices.
Semiconductor memory devices with the IIL configuration are of the bipolar type including bipolar integrated circuits in order to isolate semiconductor elements involved from one another and simplify the manufacturing steps therefor. Such bipolar semiconductor memory devices include an injection coupled memory cell having common base PNP transistors and common emitter NPN transistors in composite form.
In semiconductor memory devices with that IIL configuration the structure by which the semiconductor elements involved are isolated from one another can be simplified and the electrical interconnection between the semiconductor elements can be made by a simple wiring pattern. Thus those semiconductor memory devices are advantageous in that the manufacturing process can be simpler than that for an integrated circuit having general bipolar transistors assembled thereinto. Semiconductor memory devices with the IIL configuration which have been proposed have included the lateral transistor assembled into the longitudinal transistor. However it has been difficult to obtain a high performance from such conventional semiconductor memory devices because the lateral transistor has a low in efficiency for injection of carriers and the frequency characteristic thereof is poor.
Accordingly it is an object of the present invention to provide a new and improved semiconductor memory device which is highly efficient in performance and including transistors having a high efficiency of injection of carriers and having a good frequency characteristic.